Just-About Usable Computer ISA Spec

A fantasy 8-bit Harvard-architecture kinda-RISC-but-kinda-CISC CPU design.

A JAUC interpreter written in Java

Memory

The JAUC architecture allows for 65528 instructions in program address space and up to 64KiB of data address space.

The first 8 words of the program space are reserved for 8 interrupt vector addresses. If the vector address is zero, program execution is immediately halted for inspection in a debugger or monitor.

Program execution begins at program address 8.

Registers

There are 8 8-bit general-purpose registers. The 1st register is hardwired to zero. The 8th general-purpose register is 16 bits wide. The 8th register is used by the LLJ and ULL instructions for long-distance jumps.

There is an internal 256-word stack used for 16-bit procedure return addresses. A stack interrupt is triggered when this stack overflows or underflows.

There is another internal 256-byte general-purpose stack usable by programs. A stack interrupt is triggered when this stack overflows or underflows.

The Instruction Pointer (IP) register is an internal register pointing to the current instruction being executed. It cannot be accessed outside of jump instructions.

The Interrupt Return Pointer (IRP) register is an internal register that is used to store the return address for an interrupt handler. It cannot be accessed by user code.

Interrupts

When an interrupt is triggered, the current instruction's address plus one is pushed to the internal return address stack. If an interrupt occurs during an interrupt handler, a double-fault occurs and the CPU resets. A debugger or monitor may catch the double-fault and halt execution without resetting the CPU.

Interrupt List

Instruction Encoding

All instructions are 16 bits wide.

For A-type instructions, the first 5 bits of the first byte is the instruction opcode and the final 3 bits of the first byte is the target register. The second byte specifies two operand registers encoded in each nibble. An operand register nibble higher than 7 will trigger an invalid instruction interrupt.

For I-type instructions, the first 5 bits of the first byte is the instruction opcode and the final 3 bits of the first byte is the target register. The second byte is an immediate operand.

For J-type instructions, the first 5 bits of the first byte is the instruction opcode and the final 3 bits are set to zero. A J-type instruction with the final 3 bits not set to zero will trigger an invalid instruction interrupt. The second byte is an immediate operand.

Opcode Listing

Below is a list of opcodes numbers, their types, their assembler mnemonic, and a description of their effect.

Only the low byte of register 8 is directly usable. Register 8's high byte can only be accessed by bit shifting.